Abstract
Electrical measurements are made either by directly contacting the test structure on a silicon wafer to the test equipment as shown in Fig. 2.1 or after dicing and packaging the test structure. The design of test structures is therefore closely coupled to the method of interfacing to the test equipment and the capabilities and limitations of the test equipment itself. Design and test efficiency is improved by standardizing the footprints of each class of test structures and maintaining a high degree of commonality among them. Many of the test structures for MOSFET and CMOS circuit characterization may be implemented at the first level of metal. During technology development and manufacturing, feedback from such test structures early in the process cycle can help reduce the fabrication cost of CMOS products. In this chapter, the essential elements of electrical test structures in CMOS technology are introduced. Special emphasis is placed on integrating the design effort with silicon area usage constraints and test requirements. The concepts presented here for achieving efficiency in design, data acquisition, and analysis are followed throughout the book.
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