Test Set Partitioning in Multilayerd SoCs for Thermal Aware Test Scheduling

Abstract

Test Partitioning is an important step in VLSI Testing. The testing of any VLSI circuit should be fast, cheap and complete. If the testing is performed in one step, huge amount of heat is released since it is done at speed. Testing involves management of temperature as well. Test partitioning is an important step resorted to in such cases. Since the circuits involve thousands of devices, testing is a time consuming process. Partitioning for 3D SoC testing is proposed in this paper to arrest the temperature rise and testing time. In 3D SoCs, testing accumulates much more heat than planar circuits since heat gets trapped in layers. Here an attempt is made to manage temperature rise during testing of 3D SoCs by partitioning the test sets. Partitioning refers to application of tests in two or more chains rather than one step. This consumes more time hence some interleaving is also required to be done. Interleaving refers to grouping of different test sets so that at one time different chips are tested together. An algorithm for the same is proposed and the temperature rise of each core is monitored. It is also compared with the temperature rise of cores in case of scheduled testing and a good improvement is noticed. It is also compared with standard work. The simulation is done on HotSpot-6.02 using standard benchmark circuits. Apart from the time requirement, heat is also a byproduct of testing which can create hotspots and harm the chip. Test partitioning is done so as to keep the temperature rise of core during the process under check as it will inadvertently give out excessive heat. Partitioning during test is undoubtedly a large area of research. In this paper attempt is made to contribute an algorithm for test set partitioning while maintaining the temperature under check and also limiting the time required.