Abstract

Extended compatibilities scan tree technique reduces test application time and test power drastically during shifting-in the same test data to the compatible scan cells by employing NOT and XOR functions. However, both its test response data volume and its wire length are increased. This paper proposes a novel construction for extended compatibilities scan tree to reduce test response data volume and wire length. The proposed technique comprises three processes including regrouping scan cells, reordering the cliques of scan cells and overturning the scan tree for the original extended compatibilities scan tree. Experimental results show that our approach achieves lower test response data volume and shorter wire length while keeping almost the same test application time, test input data volume, test power and area overhead compared with the previous construction. Experimental results on ISCAS'89 benchmark circuits show that the test response data volume is reduced 30.16% at most; and the wire length is reduced 50.73% in average.

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