Abstract
In this paper, a design of a test processor ASIC employing a probabilistic approach is presented. The test processor chip is computer programmable. It consists of linear feedback shift register (LFSR) which can select one of 16 polynomials and set user programmable need for every test set, signature analyzer and 3 built-in RAMs and other control circuitry. It is capable of generating random numbers and applying them to the circuit under test (CUT) and then retrieve the responses from the CUT. It can generate a signature by compressing the response data and detect circuit faults by comparing this signature with that of a good CUT. This ASIC can be used to design a low cost IC tester of reliable performance.
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