Test Optimization in Memristor Crossbars Based on Path Selection

Abstract

Memristors have recently shown significant promise in designing memory and logic subsystems. A 2D-crossbar architecture built with memristor arrays provides a convenient platform for storing multivalued memory states by utilizing the analog variation of current-induced resistance through these cells. The integration of CMOS components with non-CMOS memristor cells further enhances the scope of their applications to various complex system designs. However, present-day memristors by virtue of their inherent structure are prone to various manufacturing defects and sensitive to operational modalities. Existing techniques for testing memristor arrays are either ad hoc in nature or suited for application-specific designs with little concern for optimizing test time. In this work, we envisage a 2-D memristor crossbar as a network and identify certain paths that are suitable for fault sensitization. For full-size square and rectangular memristive crossbars, the proposed method optimizes test time using a path-based technique guided by maximum matching in bipartite graphs. An integer linear programming (ILP) formulation is then used to solve the problem for a general crossbar, either full or incomplete. Simulation results with LTspice demonstrate the effectiveness and superiority of the method to the prior art in terms of test time and fault coverage.