Test of data retention faults in CMOS SRAMs using special DFT circuitries

Abstract

Data retention faults in CMOS SRAMs are tested by sensing the voltage at the data bus lines. Sensing the voltage at one of the data bus lines with proper DFT (design for testability) reading circuitry allows the fault-free memory cells to be discriminated from the defective cell(s). Two required DFT circuitries for applying this technique are proposed. The cost of the proposed approach in terms of area, test time and performance degradation is analysed. A CMOS memory array with the proposed DFT circuitries has been designed and fabricated. The experimental results show the feasibility of this technique.