Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel Scan Structures

Abstract

Test technologies for integrated circuits have traditionally tried to maximise test data compression rates, because these are essential for keeping test time and costs low. However, power consumption during the test process is a problem that has been addressed on recently. Excessive power consumption may result in thermal stress and increased voltage drops within the circuit, which implies increasing signal delays. Thereby even fully-functional circuits may fail during delay testing. Therefore, in this paper a flexible concept is proposed which combines test pattern compression using a scan controller concept and reduction of power consumption during the fast capture cycles of transition delay tests. Essentially, this concept consists of a Greedy algorithm, which fills X-rich pattern with 0s or 1s step-by-step, and an event-driven logic and power consumption simulator, which calculates the costs of these steps. The implemented concept is applied to X-rich test sets of ISCAS'89, ITC'99 benchmarks and OpenSparc cores. Results show a best case with 96 percent test data reduction combined with 32 percent less peak capture power. With this concept it is also possible to reduce the peak power for shift-in, launch and shift-out cycles by over 50 percent.