Test bench development for acquisition module FPGA of Ultrasonic flow meter

Abstract

This paper describes the development of a test bench for FPGA in the acquisition module of Ultrasonic flow meters. The test bench provides a very useful platform to test the FPGA code and locate the errors. It includes verification of the dual port memories and its functionality. It also is very useful for comparing current output with the desired one. The test bench gives errors where there is a flaw in the functionality or any module dysfunction. It gives high testability to the FPGA of acquisition module. The basic operation to be performed is the development of test bench which is written in Altera Quartus II and simulated using Modelsim Altera software. Simulation result for one of the test cases is described here along with the test bench code for the same.