Abstract
This paper presents the test-beam results of a monolithic pixel-detector prototype fabricated in 200nm Silicon-On-Insulator (SOI) CMOS technology. The SOI detector was tested at the CERN SPS H6 beam line. The detector is fabricated on a 500 μm thick high-resistivity float-zone n-type (FZ-n) wafer. The pixel size is 30 μm × 30 μm and its readout uses a source-follower configuration. The test-beam data are analysed in order to compute the spatial resolution and detector efficiency. The analysis chain includes pedestal and noise calculation, cluster reconstruction, as well as alignment and η-correction for non-linear charge sharing. The results show a spatial resolution of about 4.3 μm.
Highlights
A high-precision position measurement is required for vertex and tracking detectors at future linear colliders with a resolution of about 3 μm for the vertex detector and 7 μm for the tracking detector
In comparison to most hybrid pixel detector, there is no need for mechanical bumpbonding of sensor and readout electronics, such that smaller pixels and less complex detector systems can be produced
The reference tracks from the telescope have been reconstructed in Marlin (Modular Analysis and Reconstruction for the LINear collider) framework while the actual analysis has been implemented in standalone software developed for the SOI detector prototype
Summary
A high-precision position measurement is required for vertex and tracking detectors at future linear colliders with a resolution of about 3 μm for the vertex detector and 7 μm for the tracking detector. The Silicon-On-Insulator (SOI) CMOS implements a SiO2 insulator (BOX - buried oxide) between a thick high-resistivity substrate and a thin low-resistivity silicon layer Such a structure provides the possibility to fabricate a monolithic pixel-detector with a sensor matrix on the substrate and readout electronics above the BOX in an thin outer silicon layer. The recent results of pixel detectors implemented in 200 nm Lapis SOI technology [2] show that this particular process seems to be a very good candidate for detectors on future linear colliders, since the benefits provided by the SOI technology allows to fulfil demanding requirements of space and time resolution. Systems in SOI technology combine monolithic pixel detector advantages among with the high signal from a fully depleted structures as in hybrid detectors. Scheme of an SOI CMOS structure working as a particle detector
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