Test Application for Analog/RF Circuits With Low Computational Burden

Abstract

In this paper, we propose an adaptive test strategy that tailors the test sequence with respect to the properties of each individual instance of a circuit. Reducing the test set by analyzing the dropout patterns during characterization and eliminating the unnecessary tests has always been the approach for high volume production in the analog domain. However, once determined, the test set remains typically fixed for all devices. We propose to exploit the statistical diversity of the manufactured devices and adaptively eliminate tests that are determined to be unnecessary based on information obtained on the circuit under test. Test time information is incorporated in the method to yield short test time. The proposed methodology is computationally efficient and imposes very little overhead on the tester. We compare our results with other similar specification-based test reduction techniques for a low noise amplifier (LNA) circuit and an analog industrial circuit. Results show 85% test quality improvement for the same test time or 24% test time reduction for the same test quality for the LNA circuit. Moreover, near zero defective parts per million is achieved for the industrial circuit.