Abstract
FinFET transistors are commonly acknowledged as the most promising technology able to play a crucial role to route the development of rapidly growing modern silicon industry. Embedded memories, based on FinFET transistors, lead to new defect types that can require new embedded test and repair solutions. To investigate FinFET-specific faults, the existing fault models and detection techniques are not enough because of the spatial structure of FinFET transistors. This paper presents the results of the comprehensive study carried out for FinFET-based memories based on a new fault modeling and test algorithm creation strategy. The proposed solution is validated on several real FinFET-based embedded memory technologies.
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