Ternary Logic Design Approach - From CMOS to CNTFET

Abstract

The goal of this review is to offer a broad study on the ternary logic designs based on CMOS (complementary metal-oxide-semiconductor) and CNTFET (carbon nanotube field effect transistor) suitable for energy efficient and high-performance VLSI design. Performance investigation of the ternary logic-based designs will be the primary emphasis as the ternary logic is a good substitute for the conventional binary logic among all the multiple-valued logics because it permits simple and power efficient digital design owing to the lessen chip area and circuit overhead due to interconnects. The usefulness of this paper lies in the field of academic and research related to low power and high-speed VLSI design, and nano-scale devices. A brief summary of ternary logic designs based on CMOS and CNTFET is presented. This study enables the reader to clear basic concepts about the ternary logic designs and their performance analysis. Keywords: CMOS, carbon nanotube field effect transistor (CNTFET), multi-valued logic (MVL) design, ternary logic, HSPICE