Ternary input signal to binary bit output conversion CMOS integrated circuit design using neuron MOSFETs

Abstract

Multiple-input floating gate MOSFET also known as a neuron MOSFET or neural transistor and floating gate potential diagrams have been used for the conversion of ternary-valued input into corresponding binary output in CMOS integrated circuit design environments. The method is demonstrated through the design of a circuit for conversion of ternary inputs 00 to − 1− 1 (decimal 0 to − 4) and 00 to 11 (decimal 0 to + 4) into the corresponding binary bits in a standard 0.5 μm digital CMOS technology. The physical design of the circuit is simulated and tested with SPICE using MOSIS BSIM3 model parameters. The maximum propagation delay of the output is nearly 1.2 μs. The conversion method is simple and compatible with the present CMOS process. The circuit could be embedded in digital CMOS VLSI design architectures.