Temperature Effects in SET/RESET Voltage–Time Dilemma in Pr0.7Ca0.3MnO3-Based RRAM

Abstract

To understand the voltage–time dilemma in Pr0.7Ca0.3MnO3 (PCMO)-based resistive random access memory, we present switching transient currents for 10 ns–1 s for both SET and RESET. Three stages are observed during SET: 1) fast current (<100 ns) increase; 2) weak current increase; and 3) abrupt current increase to compliance. During RESET, four stages are observed: 1) fast increase in current; 2) fast reduction in the current; 3) current saturation; and 4) power law reduction of current with time. Such behavior is qualitatively independent of temperature. A qualitative mechanism is proposed. Furthermore, three implications on device performance are presented. First, the SET/RESET switching speed is limited by heating timescale to ~100 ns. Second, both SET and RESET read-disturb behaviors show exponential dependence on lower applied bias although RESET starts at lower bias in comparison to SET. This enables better immunity to read-disturb for high resistance state (HRS) on SET polarity. Third, SET transients are ambient temperature dependent, unlike RESET. This is consistent with the mechanism that during the SET process, the low current HRS does not produce a strong self-heating and, hence, depends upon ambient temperature. In comparison, during RESET process low-resistance state produces high current that enables intrinsic self-heating. Internally, generated high heat during RESET produces weak dependence on ambient temperature.