Abstract
Thermal capacitances are required to describe the fast dynamic thermal behavior in the silicon-on-insulator (SOI) devices. This article presents a physical model based on the ac technique, together with the characteristic thermal frequency determination through the frequency response of the output conductance, for calculating the thermal capacitance of single-finger and multi-finger SOI-MOSFETs. The model accounts for the total gate width and substrate temperature, making evident the augmented thermal coupling when multi-fingers are used. The thermal capacitances and the corresponding time constants, extracted from a variety of gate widths and number of fingers, are correctly predicted up to a substrate temperature of 150 °C.
Highlights
Silicon-on-insulator (SOI) MOSFETs, having a buried oxide layer thicker than 100 nm, suffer from obstruction of the heat flow towards the substrate [1], [2]
This model is based on the following analogy between electrical and thermal magnitudes: The temperature rise in the device channel, ΔTc, above the substrate temperature, Tsub, is the “voltage drop” when the “current” flowing through the circuit is the electrical power dissipated, P, in the device (i.e. ΔTc = ZthP, with 1/Zth = 1/Rth + jωCth)
In contrast to [19], the thermal time constant diminishes as the substrate temperature rises, this dependence being more intense in single-finger devices and when the total gate width increases
Summary
Silicon-on-insulator (SOI) MOSFETs, having a buried oxide layer thicker than 100 nm, suffer from obstruction of the heat flow towards the substrate [1], [2]. The typical thermal model for the temperature rise in devices, induced by self-heating effects, consists of the equivalent circuit shown, with the thermal resistance, Rth, and capacitance, Cth, being connected in parallel. This model is based on the following analogy between electrical. A model for the thermal capacitance is proposed, to be implemented in circuit simulators, which is valid when the thermal coupling increases by the use of multi-finger devices [12], and that includes the substrate temperature and total gate width dependencies.
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