Temperature Dependence of 55 nm Gate Oxide, 2.3 kV SiC Power JBSFETs With Linear, Hexagonal, and Octagonal Cell Layouts

Abstract

The electrical characteristics of 2.3-kV 4H-SiC power Junction Barrier Schottky Field-Effect Transistors (JBSFETs) fabricated with 55-nm gate oxide thickness are reported as a function of temperature for the first time. The behavior of three cell topologies (linear, hexagonal, and octagonal) is compared. Excellent JBSFET characteristics are demonstrated up to 150 °C. The ON-resistance was found to increase by 45% from 25 °C to 150 °C for the linear and hexagonal cell layouts, which is much less than the 100% increase previously reported for silicon carbide (SiC) power MOSFETs. The threshold voltage decreases with temperature but remains above 1.2 V even at 150 °C for all cases. The third-quadrant current flow via the integrated JBS diode is confirmed to suppress body diode conduction at all temperatures. The leakage current remains below <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1~\mu \text{A}$ </tex-math></inline-formula> even at 150 °C despite the presence of the Schottky contact in the JBSFET structure due to optimum JBS diode design. The octagonal cell topology is shown to exhibit the best figures of merit (FOMs) FOM[ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ \mathrm{R}_{ \mathrm{\scriptscriptstyle ON}}{}^{\ast } \mathrm{C}_{ \mathrm{\scriptscriptstyle GD}}$ </tex-math></inline-formula> ] and FOM[ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ \mathrm{R}_{ \mathrm{\scriptscriptstyle ON}}{}^{\ast } \mathrm{ Q}_{ \mathrm{\scriptscriptstyle GD}}$ </tex-math></inline-formula> ] even at elevated temperatures. The observed device behavior is explained using device analytical modeling. The analytical modeling reveals that the reduced rate of increase in ON-resistance with temperature for the 2.3-kV SiC JBSFETs is due to the relatively large source contact resistance produced by the lower (900 °C) contact anneal temperature. The lower anneal temperature is required to simultaneously make the Schottky contact for the JBS diode.