TEM characterization of dislocation reduction processes in GaAs/Si

Abstract

A high density of interfacial dislocations are needed at the GaAs/Si interface to alleviate the 4% lattice mismatch between GaAs and Si. Some remnant dislocations thread through the epilayer and follow the growth interface. Current growth methods are not able to obtain acceptable threading dislocation densities (104 – 105) for devices. Many methods can be used to reduce the number of threading dislocations which include misorienting the substrate to enhance the slip of dislocations on specific [110]{111} planes, annealing during and after growth, and adding strained layer superlattices (SLS's) to block dislocations. Conventional TEM (CTEM), performed using a JEM 100c, has been used to characterize threading dislocations in the epilayer of a GaAs/Si material where in situ thermal annealing and SLS's force dislocation reactions and thereby reduce the threading dislocation density. Using TEM we have viewed dislocations under many two-beam diffraction conditions and with the help of a stereogram have determined their Burgers vectors (b), line directions (u) and habit planes (R).