Abstract
With technology scaling, the trend for high performance integrated circuits is towards higher power dissipation, higher operating frequency and lower power supply voltages. This causes a dramatic increase in power supply current being delivered through the on-chip power grid and is recognized in the International Technology Roadmap for Semiconductors as one of the difficult challenges. The design of appropriate power grids and the addition of decoupling capacitance has become crucially important in order to control power-grid-induced noise. In this paper, we show analytical relationships between noise and various technology parameters, and we show the resulting trends in noise based on current roadmap predictions.
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