Technology optimized fixed-point bit-parallel multiplier for LUT based FPGAs

Abstract

Modern day field programmable gate arrays (FPGA) have look-up tables (LUT) as inherent basic logic elements. With FPGAs fast moving from prototype designing to low and medium volume productions, there is an increased need for efficient utilization of these FPGA primitives. Unfortunately majority of the work concerned with FPGA implementations focus only on the technology independent (architectural) optimizations that can be done at the top level of the logic synthesis process. Once a design has been modified architecturally, its behavioral description is fed to the synthesizer that drives the logic synthesis process as per the desired cost function. Any technology dependent optimization done by the synthesizer is thus hidden from the designer. In this paper we consider the technology dependent optimization of the fixed-point bit-parallel multiplier on LUT based FPGAs. We perform technology dependent optimizations prior to the design entry phase and then use instantiation based coding styles to ensure that the optimizations remain preserved throughout the synthesis process. We have compared our implementation results against various fixed-point multipliers reported in [28]. Our implementations show substantial improvement in terms of resources utilized, critical path delays and dynamic power dissipation. An important feature of technology dependent optimizations is that it results in a simultaneous improvement of all the performance parameters. This is in contrast to the technology independent optimizations where there is always an application-driven trade-off between different performance parameters.