Technology Mapping for FPGAs

Abstract

As mentioned in Chapter 1, the CAD system for a given FPGA performs several tasks needed to arrive at the final implementation of a circuit. This chapter focuses on the logic synthesis step in the CAD system, which consists of two separate phases called logic optimization and technology mapping. As illustrated in Figure 3.1, the original logic network is first manipulated by a logic optimization program, which produces an optimized network that is functionally equivalent to the original network. Logic optimization for FPGAs involves the same tasks as for other environments. Since a number of well-known logic optimization techniques have been described in several publications, we will only discuss it briefly in this chapter.