Technology mapping algorithm for heterogeneous field programmable gate arrays

Abstract

To maximise device utilisation, a heterogeneous field programmable gate array (FPGA) provides either an array of homogeneous lookup tables (LUTs) of different sizes or an array of physically heterogeneous LUTs. It is shown that heterogeneous FPGAs have a significant number of desirable attributes. A technology mapping algorithm is proposed for heterogeneous FPGAs. The technology mapping problem is first formulated as a flow network problem. Then, an algorithm based on the min-cost max-flow algorithm is presented to select a proper set of feasible LUTs for various objectives. Two objectives: (i) the minimum number of LUTs; and (ii) the total area composed of LUTs and routing area are discussed. The algorithm is tested on the MCNC benchmark circuits and produces better characteristics than existing LUT-based FPGA mapping algorithms.