Technology Independent ASIC Based Time to Digital Converter

Rui Machado,Jorge Cabral,Filipe Serra Alves,Alvaro Geraldes

doi:10.1109/access.2020.3034522

Rui Machado, Jorge Cabral + Show 2 more

Open Access

https://doi.org/10.1109/access.2020.3034522

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Abstract

This paper proposes a design methodology for a synthesizable, fully digital TDC architecture. The TDC was implemented using a hardware description language (HDL), which improves portability between platforms and technologies and significantly reduces design time. The proposed design flow is fully automated using TCL scripting and standard CAD tools configuration files. The TDC is based on a Tapped Delay Line architecture and explores the use of Structured Data Path (SDP) as a way to improve the TDL linearity by homogenizing the routing and parasitic capacitances across the multiple TDL's steps. The studied approach also secures a stable, temperature independent measurement operation. The proposed TDC architecture was fabricated using TSMC 180nm CMOS process technology, with a 50MHz reference clock and a supply voltage of 1.8V. The fabricated TDC achieved an 111ps RMS resolution and a single-shot precision of 54ps (0.48 LSB) and 279ps (2.51 LSB), with and without post-measurement software calibration, respectively. The DNL across the channel is mostly under 0.3 LSB and a maximum of 8 LSB peak-to-peak INL was achieved, when no calibration is applied.

Highlights

Time-to-Digital Converters (TDC) have been extensively used in positron emission tomography (PET) and other experimental physics areas [1]–[3], and in high precision metrology equipment [4]
Current state-of-the-art Application Specific Integrated Circuits (ASIC) TDCs have already achieved precisions in the range of tens of picoseconds [5]–[13]. These advances have been escorted by a strong technological evolution in Field Programmable Gate Arrays (FPGA), which have become a platform of interest for TDC research applications, due to its low cost, fast development cycle and large flexibility
When analyzing ASIC and FPGA TDCs architectures, the major difference stands on the resolution defining logic element

Summary

Introduction

Time-to-Digital Converters (TDC) have been extensively used in positron emission tomography (PET) and other experimental physics areas [1]–[3], and in high precision metrology equipment [4]. Current state-of-the-art Application Specific Integrated Circuits (ASIC) TDCs have already achieved precisions in the range of tens of picoseconds [5]–[13]. These advances have been escorted by a strong technological evolution in Field Programmable Gate Arrays (FPGA), which have become a platform of interest for TDC research applications, due to its low cost, fast development cycle and large flexibility. When analyzing ASIC and FPGA TDCs architectures, the major difference stands on the resolution defining logic element. When designing an ASIC, the possibility to create custom cells adds different TDC architecture implementation options, and increases the overall design complexity

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