Technologies for (sub-) 45nm Analog/RF CMOS ¿ Circuit Design Opportunities and Challenges

Abstract

The new process module and device architecture options emerging for (sub-) 45nm CMOS lead to both opportunities and challenges for analog/RF circuit design. These will be discussed both at the device level and circuit level for two competing architectures (planar bulk CMOS versus FinFETS), for different gate stacks and mobility enhancement techniques. Very high cutoff frequencies will be demonstrated for planar bulk CMOS devices, while FinFETs exhibit high voltage gain and excellent matching performance. As a result, FinFETs will be shown to be better suited for analog baseband design and to have acceptable RF performance in the 1-10 GHz range, while planar bulk CMOS outperforms the FinFETs for sub-circuits above 10 GHz.