Technological enhancers effect on Ni0.9Co0.1 silicide stability for 3D sequential integration

Abstract

Abstract3D sequential integration is a promising alternative to conventional scaling down approach: by stacking transistors level on top of each other, benefits on device density and performance are achieved. However, although the thermal processing of top transistors is currently restricted in order to avoid bottom CMOS degradation, it has been highlighted that Ni0.80Pt0.10 silicide source/drain (S&D) contact remains the most sensitive element to the thermal budget, especially on raised Si0.7Ge0.3:B S&D for pMOS transistors. In this context, a complete and systematic study on self‐aligned silicide (SALICIDE) process has been proposed: alternative metallization as well as source and drain surface pre‐treatments have been carried out. Indeed, a novel Ni‐based silicide, the Ni0.9Co0.1 provides a better stability on unpatterned 300 mm wafers. This stability has been further improved when combined with epitaxial silicon capping layer (Si‐Cap) and Si0.7Ge0.3:B S&D pre‐amorphization implant (PAI) using Ge beam. For the first time, a successful Ni0.9Co0.1 SALICIDE implementation has been demonstrated on pMOS planar FDSOI transistor with both PAI and Si‐Cap. Moreover, the presence of Si‐Cap contributes to reduce silicide roughness and limits Ge partition that damage Si0.7Ge0.3:B S&D. (© 2016 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)