Abstract
Existing techniques for path delay fault (PDF) diagnosis prune fault-free candidates using nonfailing patterns but fail to reduce the size of suspect set significantly. This paper presents two alternative techniques that can be applied in a postprocessing manner to further reduce the suspect set by prioritizing paths using only the failing patterns. Experimental results on the ISCAS benchmarks demonstrate that they are time and memory efficient.
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More From: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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