Abstract
This paper presents two techniques for reducing phase noise in recirculating delay-locked loops (DLLs) and extends recently developed theoretical results to optimize the performance of a recirculating DLL prototype CMOS IC incorporating the techniques. One of the techniques reduces 1/f noise in both the voltage-controlled oscillator (VCO) and bias circuitry through hard periodic switching of key transistors. The other technique maximizes the phase noise suppression achieved by periodically switching in a clean reference pulse to reset the VCO phase noise memory. Theoretical results are used to optimize the loop filter and establish several general design guidelines for recirculating DLLs. Measured performance data from the fabricated IC with and without the techniques enabled closely support the theoretical predictions.
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