Technique for Increasing the Output Impedance of CMOS Regulated Cascode Circuits

Abstract

A technique is proposed for the design of a modified CMOS regulated cascode having an output impedance significantly greater than that of a conventional regulated cascode. Simulation results for an illustrative design, operating at 10[Formula: see text][Formula: see text]A from a 1[Formula: see text]V supply, show an increase in output resistance from 636 M[Formula: see text] and output bandwidth of 55[Formula: see text]kHz for a conventional circuit to 6.68 G[Formula: see text] and 389[Formula: see text]kHz, respectively, for the proposed design.