Abstract
This paper studies the realization of the high level synthesis from system behavioral (algorithmic or functional) description of circuits to structural description of RTL and logic level. Based on Xilinx-FPGA library, the structural description is mapped to technology-dependent ASIC, and FPGA chips are generated. The main points in this paper include the technical decision of each sub-system in a VHDL high level synthesis system HLS/BIT. The system is realized on SUN SPARC 2, and correct running results are given.
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