TCAM core design in 3D IC for low matchline capacitance and low power

Abstract

Ternary Content Addressable Memory (TCAM) has been an emerging technology for fast packet forwarding, commonly used in longest prefix match routing. Large table size requirements and wider lookup table data widths have led to higher capacity TCAM designs. However, the fully parallel characteristic of TCAM makes large TCAM design more challenging and limits its capacity due to intensive power consumption. This paper proposes 3D IC technology as a solution to reduce the power consumption by reducing the interconnect capacitances of TCAM. In 3D IC, multiple wafers are stacked on top of each other, and the tiers are vertically connected through 3D vias. 3D vias reduce metal interconnect lengths and parasitic capacitances, resulting in power reduction. In this paper, 3D vias are used to replace matchlines, whose transition during parallel search operations is a major source of high power consumption in TCAM. An analysis of parasitic interconnect capacitance has been done using a quasi-static electromagnetic field simulation tool, Ansoft’s Q3D Extractor, on a TCAM memory core in both conventional 2D IC structure and 3D IC structure with the process parameters of the MIT Lincoln Labs 0.18um FDSOI process. Field analysis and spice simulation results using a capacitance model for interconnects show that a 40% matchline capacitance reduction and a 23% power reduction can be achieved by using a 3-tier 3D IC structure instead of the conventional 2D approach.