Abstract
Full fabrication process of nanoscale vacuum channel and gate-all-around nanowire transistors at the 45, 32 and 22 nm technology nodes was simulated in Silvaco TCAD. Comparative analysis of operation modes was made on the basis of the obtained structures. It was shown that nanoscale gate-all-around transistor has sufficiently low power consumption while vacuum channel field effect transistor makes it possible to achieve performance that exceeds performance which can be obtained from the transistor with semiconductor channel. The combination of the above technologies can serve as approach to the creation of low-power and high-speed nanoscale vacuum devices using established complementary metal-oxide-semiconductor (CMOS) technology.
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