Task level behavioral hardware description

Abstract

A synthesizable VHDL subset is defined with constructs focusing on synchronization and communication. The VHDL signal concept is replaced by new object types representing mutual exclusion data, communication data and events. Also two other objects are introduced performing labelling for process and task identification. The task level analysis suggests an architectural mapping on architecture modules. After the mapping the description is translated into standard IEEE VHDL, replacing all special objects by the VHDL signal object. A RTL level synthesis may be performed on every hardware module consisting of a datapath and one controller.