Abstract
Phosphorus-doped SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> is frequently used as a dielectric coating in silicon integrated circuits. It is important that windows in this dielectric have sufficiently tapered walls so that the subsequent metallization has good step coverage. It is shown here that tapered windows can be made in both Nitrox-deposited ∼ 1-percent phosphorus-doped SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> and Silox-deposited ∼ 7-percent phosphorus-doped SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> as well as undoped SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> by an ion implantation which produces a thin damaged layer at the top of the oxide. The damaged layer etches at a faster rate than the undamaged oxide. This fast-etching layer undercuts the photoresist which serves as the etching mask and results in window walls having slopes in the range of 30-40° with respect to the wafer surface. Tapering windows by ion implantation is a dependable process that gives reproducible results without having to rely on the art of photoresist liftoff methods.
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