Taking Silicon to the Limit: Challenges and Opportunities

Abstract

Silicon-based CMOS transistors can be scaled well into the sub-10 nm regime. However, new materials and processes, in conjunction with advanced transistor structures, will be needed for nanometer-scale MOSFETs to meet performance specifications in the International Technology Roadmap for Semiconductors (ITRS). This paper discusses challenges for achieving target performance metrics at the end of the Roadmap, and approaches to overcoming them.