TABS: Temperature-Aware Layout-Driven Behavioral Synthesis

Abstract

With rising power densities in modern VLSI circuits, thermal effects are becoming important in the design of ICs. Elevated chip temperatures have an adverse impact on performance, reliability, power consumption, and cooling costs. To ensure adequate thermal management, all phases of the design flow must account for thermal effects on their design decisions. We present a two-stage simulated annealing-based high-level synthesis technique that combines power minimization with temperature-aware scheduling, binding, and floorplanning. In our technique, the first stage of the simulated annealing algorithm creates a low-power solution, which is then iteratively improved by the second stage to minimize estimated on-chip peak temperature using accurate module-level temperature estimation. We show that minimizing average power alone does not guarantee minimal peak temperatures. However, our approach consistently finds solutions that have lower on-chip peak temperatures and uniform on-chip temperature distributions, compared to a traditional low-power synthesis methodology that minimizes average power. Experiments show that our method reduces peak temperatures on average by 12% and up to 16%, compared to a traditional low-power synthesis algorithm that minimizes average power. These improvements in chip-level temperature distributions are achieved with a modest increase in chip area of under 15% on average.