Table-Free Seed Generation for Hardware Newton–Raphson Square Root and Inverse Square Root Implementations in IoT Devices

Abstract

Restrictions inherent to processors used in the Internet of Things (IoT) devices or the need for area reduction in massively parallel processing systems for artificial intelligence lead to the search of tradeoffs between precision and area in arithmetic operations. In this sense, simple precision enables to save area and to speed up computations when no higher precision is required. On the other hand, iterative methods such as Newton–Raphson’s or Goldschmidt’s allow to reduce or remove the use of memory tables. In these methods, the selection of the initial value or seed is critical to achieve a reasonable precision using the lowest possible number or iterations. In this article, new hardware implementations of seed generators with very low-area requirements are proposed for Square Root and Inverse Square Root, while maintaining good precision, high performance, and low power consumption. A new design methodology, named successive approximation methodology (SUAM), enables to implement seed generators using only a few logic gates. The presented experimental and implementation results support the validity of the developed seed generators.