Systolic realisation of delayed two-path linear phase FIR digital filters

Abstract

A new method for high speed realisation of 1-dimensional (ID) linear phase FIR digital filter is presented. The method makes use of pipelining in systolic arrays to reduce the minimum clock cycle time, the delayed two-path structure to increase processing speed, and the symmetry of coefficients in a linear phase FIR digital filter to reduce multiplications. The resultant systolic delayed two-path digital filter structure is consisted of four systolic arrays built from one type of basic cells with nearest neighbour interconnections. The method is optimal in terms of the number of multiplications. Both input and output of the proposed filter structure can also be systolised to form an overall pure systolic structure. The proposed digital filter structure can provide a speed improvement of 32 times as compared to that of a direct realisation of the same filter using a single processor. The proposed method is attractive for high speed adaptive and nonadaptive digital filtering