Systolic polynomial evaluation and matrix multiplication with multiple precision

Abstract

The design and implementation of a systolic VLSI multiprecision polynomial evaluator and matrix multiplier is described. The use of bit-serial arithmetic allows for a very simple cell design (two registers and an accumulator) enabling a substantial number of cells to be placed on a chip. A configuration of N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> cells can evaluate N polynomials of N coefficients at N points and perform. N-width band matrix multiplication and N × N full matrix multiplication, each in linear time. Using current technology, 100 polynomials of 100 coefficients can be evaluated at 100 data points with 32 bit precision in an estimated one millisecond.