Abstract
The concept of multi-input multi-output systolic array implementation of 2-D linear-phase FIR (finite-impulse response) digital filters is introduced. It has been applied to eight cases of linear-phase FIR digital filters with factors of about four and two savings in implementation complexity, respectively, for four cases of four-quadrant symmetry and for four other cases of two-quadrant symmetry. The resulting architectures are suitable for real-time digital filtering as well as for VLSI implementation. >
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