Systolic array implementation for separable denominator two-dimensional state-space digital filters based on the reduced-dimensional decomposition

Abstract

With recent developments in integrated circuit (IC) technology and digital communication networks, the demand for efficient and high-quality conversion, transmission, and coding of high-definition images has greatly increased. For this purpose, construction of higher parallel two-dimensional (2-D) digital filtering systems based on efficient parallel processing algorithms of 2-D digital filters is necessary. This paper proposes a systolic array implementation for separable denominator 2-D state-space digital filters by applying block processing based on the reduced-dimensional decomposition. First, the 2-D state-space digital filter using reduced-dimensional decomposition is described. Next, the 2-D state equations are derived by applying block processing and its properties are shown. As a result, the reduced-dimensional decomposition suitable for systolic array implementation is shown. Then the systolic array implementation corresponding to derived state equations is proposed and its effectiveness is evaluated. As a result, it is shown that this implementation can have not only extremely high throughput but it also greatly reduces the number of processing elements compared to other realizations. © 1997 Scripta Technica, Inc. Electron Comm Jpn Pt 3, 80(1): 69–79, 1997