Systolic architectures in curve generation

Abstract

The use of B-spline polynomials for the generation and display of smooth curves and surfaces in computer graphics is widely accepted. However, the algorithms to generate such smooth curves and surfaces using B-spline polynomials are compute-intensive. In this paper we propose systolic architectures for B-spline generation and inversion. The systolic architecture for the generation of a degree m B-spline curve is a triangular array requiring m(m + 1) 2 processing cells. A linear array is used for inversion. These architectures have been realized on an experimental hardware using six Intel 8086 microprocessor boards, for cubic B-spline curves. The architectures are studied in detail and performance results are tabulated. It is observed that a speedup of nearly six can be obtained with six processors.