System-level memory power and performance optimization for system-on-a-chip embedded systems

Abstract

Power has become a first rate design issue in microprocessor design. Power efficiency is especially critical for battery-powered embedded systems. Technology trends are making data communication, both on-chip and off-chip, more expensive relative to computation. Evaluating power-performance design trade-offs at the architectural level still requires more research study. In this dissertation, we will show how microprocessor power, especially in the memory sub-system, is consumed during program execution. We also show that the external memory system in a low power System-on-a-Chip (SOC) embedded system has significant impact on overall system power. The source of memory power consumption is due to the data transmission, bandwidth limitation, and memory access overhead. We review and summarize the current research work on low power microprocessor architecture design in academic research community and in industry world. The work includes power modeling, power estimation tools and power optimization techniques. In addition, we summarize different power optimization into five categories and compare their effects and impacts to the overall system. Two solutions are proposed to reduce data bandwidth and to improve the power efficiency on the external memory bus. We first propose an external bus arbitrator to schedule the external bus requests in order to achieve better bus utilization. We propose a series of power aware arbitration schemes for the external bus request scheduling. On average, we observe a 22 percent performance speed up and 13 percent power savings compared to traditional arbitration schemes. In our second approach, we present a hardware-based, programmable external memory page remapping mechanism which can significantly improve system performance and decrease the power budget on external memory bus accesses. We employ graph-coloring techniques to guide the page mapping procedure. Our algorithm can significantly reduce the memory page miss rate by 70-80 percent on average. For a 4-bank SDRAM memory system, we reduce external memory access time by 11 percent, while reducing the associated power consumed by 11 percent.