System-Level FPGA Routing for Logic Verification with Time-Division Multiplexing

Abstract

Multi-FPGA prototype design is widely used to verify modern VLSI circuits, but the limited number of connections between FPGAs in a multi-FPGA system may cause routing failure. Therefore, using time-division multiplexing (TDM) technology, multiple signals are transmitted through the same routing channel to improve utilization. However, the performance of this type of system depends on the routing quality within the FPGAs due to the signal delay between FPGA pairs. In this paper, we propose a system-level routing method based on TDM to minimize the maximum TDM ratio that satisfies the strict ratio constraint. Firstly, we weight the edges and use two methods to build approximate minimum Steiner trees (MST) to route the nets. Then we propose a ratio assignment method based on edge-demand which satisfy the TDM ratio constraint. We tested our method with the benchmarks provided by 2019 CAD Contest at ICCAD and compared it with the top two. The experimental results shows that our method not only solves all problems but also achieves a good TDM ratio.