SystemC implementation of mat-core: A matrix core extension for general-purpose processors

Abstract

Technological advances in IC manufacturing provide us with the capability to integrate more and more functionality into a single chip. Today's modern processors have nearly one billion transistors on a single chip. With the increasing complexity of today's system, the designs have to be modeled at a high-level of abstraction before partitioning into hardware and software components for final implementation. This paper explains in detail the implementation of a matrix processor called Mat-Core with SystemC (system level modeling language). Mat-Core is a research processor aiming at exploiting the increasingly number of transistors per IC to improve the performance of a wide range of applications. It extends a general-purpose scalar processor with a matrix core. Like vector architectures, the extended matrix core is organized in parallel lanes. In addition to vector-scalar and vector-vector instructions, the matrix core can execute matrix-vector and matrix-matrix instructions. Furthermore, for controlling the execution of vector/matrix instructions on the matrix core, this paper extends the well known scoreboard technique.