Systematic root cause analysis of ceria-induced defects during chemical mechanical planarization and cleaning

Abstract

As semiconductor devices become smaller, having ultra-smooth and flawless surfaces is crucial. The manufacturing of advanced devices requires strict conditions to avoid defects. These defects can lead to device failure and reliability problems. This paper presents a detailed study of defects related to ceria on SiO2 surfaces after post-chemical mechanical planarization (CMP) cleaning processes. The focus is on uncovering the primary causes of these defects, which are believed to appear in various forms: remnants, small fragments, and cerium-modified layers. The investigation found no traces of ceria remnants in atomic force microscopy phase images, suggesting they might have been eliminated during cleaning. Yet, small ceria particle fragments were detected on the SiO2 films. These fragments, likely created during polishing, adhere strongly to the SiO2, resisting removal by brush scrubbing. Moreover, the research revealed a cerium-modified layer on the SiO2 surface, formed by the chemical interaction between ceria particles and SiO2 films during polishing. Scanning Electron Microscopy-Energy Dispersive X-ray (SEM-EDX) mapping showed Ce atoms in areas without visible ceria particles, confirming this layer's presence. The insights from this study provide a deeper understanding of ceria-related defects in the semiconductor manufacturing process, offering valuable information for improving residue removal and surface cleaning in post-CMP processes.