Systematic modeling of on-chip power grids with decaps in TSV-based 3D chip integration

Abstract

Efficient modeling of power supply noises is crucial for a robust power supply design, especially with increase in the size of on-chip power grids due to emerging 3D chip integration technology. As the power grid is interconnected vertically by through-silicon vias (TSVs), operational currents required by each functional device in integrated circuits (ICs) are supplied through vertical power and ground TSVs, and horizontal power grids. Fast switching speed of the devices become complicated the accurate analysis of the worst case power supply noises. In this paper, a systematic modeling of on-chip power grids with decoupling capacitors - VNCAPs - used in TSV-based chip integration technology is presented using novel equivalent decap circuit model. The equivalent circuit model will be numerically validated and integrated into an efficient modeling for impedance profile of on-chip power grids and analysis of power supply noises in TSV-based 3D chip integration technology.