Systematic Design Methodology of Broadband Doherty Amplifier Using Unified Matching/Combining Networks With an Application to GaN MMIC Design

A M Elelimy Abounemra,Fadhel M Ghannouchi,Mohammad Maktoomi,Mohamed Helaoui,Weiwei Zhang,Wenhua Chen,Fei Huang

doi:10.1109/access.2020.3046706

A M Elelimy Abounemra, Fadhel M Ghannouchi + Show 5 more

Open Access

https://doi.org/10.1109/access.2020.3046706

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Abstract

This paper presents a new design methodology for broadband Doherty architecture using the three-port input and output networks technique. The proposed topology was developed to overcome the Doherty power amplifier (DPA) bandwidth limitations. The output three-port network performs the impedance matching from any load impedance to the optimum loads for both main and peaking transistors and also combines the power delivered from the two devices at any power ratio. On the other hand, the input-splitting network is proposed for matching the input impedances of the two transistors to the source impedance. The freedom in choosing the power division ratio of the input network enables us to achieve a tradeoff between efficiency and linearity. Also, it provides a way to accomplish the phase compensation using an arbitrary phase difference between the two branches of the Doherty power amplifier and thus, helps obviate the need of the highly bandwidth limiting offset lines found in the Doherty design. A two-stage broadband Doherty power amplifier is implemented using 0.25-um GaN HEMT MMIC process to validate the proposed topology. The fabricated DPA was measured under both continuous wave (CW) and modulated signal at different operating frequencies. Across 3.3–3.7 GHz, the implemented DPA delivers a maximum output power exceeding 42 dBm, power added efficiency (PAE) over 52 % at the peak power and over 38 % in the back-off state over the operating 400 MHz bandwidth. The fully integrated circuit has a chip-size of 4.4 mm $\times\,\,3.5$ mm.

Highlights

The evolution of the wireless communication systems from the fourth generation (4G) to the fifth generation (5G) networks has accelerated significantly; opening the door to many opportunities for scientific research
The main and auxiliary transistor’s large-signal input impedances are equal to the impedances Zin,M,P(f ) and Zin,A,P(f ) at Ports 2 and 3 respectively. This means that the loads at Ports 2 and 3 have no reflection (a2 = a3 = 0) according the network lossless condition; one can deduce that the input matchingsplitting network (IMSN) S-parameters matrix can be driven as in [35], (5) shown at the bottom of the page
The Monte Carlo analysis shows that the yield of gain greater than 26 dB is 75% while the yield of power added efficiency (PAE) greater than 50% at saturation power level is 97%.To verify the new design methodology, two Doherty power amplifier (DPA) based on the threeport network are designed using the reference topology as in [35] and the new analysis proposed in this paper

Summary

INTRODUCTION

The evolution of the wireless communication systems from the fourth generation (4G) to the fifth generation (5G) networks has accelerated significantly; opening the door to many opportunities for scientific research. In [29], an GaN MMIC Doherty PA was designed using a reversed uneven power splitting network to improve the linearity performance, and it included two-section λ/4 transformer to get uniform frequency response, while in [30], a modified impedance inverter network was used to increase the bandwidth. Despite the abundance of challenges and difficulties in designing a high power MMIC Doherty amplifier, it deserves a great deal of research attention as it can help fulfill the requirement of small-cell base stations It can be used as a building block for an active MIMO transmitter.

GENERIC DESIGN METHODOLOGY

FABRICATION AND EXPERIMENTAL CHARACTERIZATION

Findings

CONCLUSION