Abstract
This paper presents a numerical study of the system unbalance and the fault impedance effect on faulted power system analysis. Two short circuit techniques, the symmetrical components and phase components algorithms are implemented and analyzed based on numerical simulations of the IEEE 13 bus test feeder. Test cases include voltage unbalance effect and fault impedance effect on during-fault voltages and currents. The results show that the during-fault voltages and currents are greatly affected by both voltage unbalance and fault impedance.
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