System on programmable chip implementation of neural network-based isolated digit recognition system

Abstract

In this article, design and implementation of an isolated digit recognition system on a NiosII soft-core processor with a CycloneII FPGA is considered. Linear predictive coefficients and Mel frequency cepstral coefficients (MFCC) are used as features and their recognition performances are compared. A multilayer perceptron (MLP) is used for classification and a self-organised feature map is employed for dimensionality reduction of features. Various MLP architectures are studied in this article and it is found that a recognition accuracy of 100% is obtained with the least computational complexity using a single-layer MLP with 10 hidden nodes for the MFCC feature. Recognition performance and convergence time for training is compared for the ‘modified’ back propagation (BP) algorithm and the BP algorithm. It is observed that the modified BP is 2.82 times faster than BP with 4% increase in recognition accuracy. A hardware accelerator is proposed for the NiosII processor for the implementation of MLP and it increases the recognition speed by a factor of 278. The technique proposed in this article is also applicable for other soft-core processors such as Microblaze and Picoblaze.