System-level optimization of NoC-based timing sensitive systems

Abstract

Communication modelling and synthesis plays an important role in the design of complex network-on-chip based timing-sensitive systems-on-chip. Trying to guarantee the observance of tim- ing constraints without detailed know-how of communication transactions might lead to unexpected results. In our previous work we have proposed a system level approach for communication modelling and synthesis to calculate hard communication deadlines based on communication delay models and on guidance of the scheduling process to take into account possible network conflicts. In this paper we combine our communication scheduling approach with global optimization techniques to perform design space exploration and/or improvement of the synthesized schedule.