System Level Modeling Methodology of Application Specific Instruction Set Processor (SIP) Using SystemC

Abstract

In recent years, the development of application specific instruction set processors (ASIP) is the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that constructing such architecture is a difficult assignment that needs skilled knowledge in distinct domains: application software development tools, processor hardware implementation, and system integration and verification. To specify the design and implementation of such systems and incorporate the functionality implemented in both hardware and software forms, we are compelled to move on from traditional Hardware Description Languages (HDLs). Since C and C++ are dominant languages used by chip architects, system engineers and software engineers today, we believe that a C++ based approach to hardware modeling is necessary. This will enable codesign, providing a more natural solution to partitioning fuctionality between hardware and software. In this paper, we discuss a design approach of SystemC (a C++ class library) for ASIP at the system-level which provides necessary features for modeling design hierarchy, concurrency and reactivity in hardware. To exemplify and validate the method we employed it to the design of a 32-bit ASIP for Hindi Text-to-Speech Synthesis developed by CEERI, Pilani (INDIA). Keywords: ASIP; System; System Level Design DOI: http://dx.doi.org/10.3329/diujst.v7i1.9647 Daffodil International University Journal of Science and Technology Vol.7(1) 2012 44-49